1. Field of the Invention
The present invention relates to an organic electroluminescent display device, and more particularly, to an active matrix electroluminescent display device.
2. Discussion of the Related Art
As information technology increases, a necessity for flat panel displays having thin profiles, lightweight, and lower power consumption has increased. Accordingly, various flat panel display (FPD) devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display devices, and electro-luminescence display (ELD) devices, have been developed.
The ELD devices make use of an electro-luminescence phenomenon in which light is generated when an electric field of certain intensity is supplied to a fluorescent substance. The ELD devices can be classified into inorganic electroluminescence display (IELD) devices and organic electroluminescent display (OELD) devices, depending upon a source that excites carriers. The OELD devices have been increasingly used due to their ability to display a wide range of wavelengths of visible light, and because of their high brightness and low voltage requirements.
In addition, since the OELD devices are a self-luminescent, they have a high contrast ratio and are suitable for ultra-thin type display devices. Since they have simple manufacturing processes, the degree of environmental contamination is relatively low. Furthermore, the OELD devices have response times of only a few microseconds (μs), thereby making the OELD devices suitable for displaying moving images. Moreover, the OELD devices have no limit for viewing angles and are stable at low temperature conditions. In addition, since the OELD devices are driven with a relatively low voltage between 5V and 15V, manufacturing and design of their driving circuits are easy.
Structures of the OELD devices are similar to that of the IELD devices, but the light-emitting theory of the OELD devices is different from that of the IELD devices. For example, the OELD devices emit light by recombination of electrons and holes, and thus they are commonly referred to as organic light emitting diode (OLED) devices.
Recently, active matrix types of IELD devices having a plurality of pixels arranged in a matrix configuration and a thin film transistor connected thereto have been commonly applied to the flat panel display devices. The active matrix type has also been applied to the OELD devices, and this is commonly referred to as an active matrix OELD device.
FIG. 1 is an equivalent circuit diagram of a basic pixel structure of an active matrix OELD device according to the related art. In FIG. 1, a pixel of the active matrix OELD device has a switching thin film transistor TS, a driving thin film transistor TD, a storage capacitor CST, and a light emitting diode (LED) E. The switching thin film transistor TS and the driving thin film transistor TD are comprised of p-type polycrystalline silicon thin film transistors. A gate electrode of the switching thin film transistor TS is connected to the gate line GL, and a source electrode of the switching thin film transistor TS is connected to the data line DL. A drain electrode of the switching thin film transistor TS is connected to a gate electrode of the driving thin film transistor TD, and a drain electrode of the driving thin film transistor TD is connected to an anode electrode of the light emitting diode (LED) E. A cathode electrode of the light emitting diode (LED) E is grounded, a source electrode of the driving thin film transistor TD is connected to a power line PL, and a storage capacitor CST is connected to both the gate electrode of the switching thin film transistor TS and the source electrode of the driving thin film transistor TD.
In the pixel structure of FIG. 1, if a scanning signal is supplied to the gate line GL, then the switching thin film transistor TS is turned ON and an image signal from the data line DL is stored into the storage capacitor CST through the switching thin film transistor TS. If the image signal is supplied to the gate electrode of the driving thin film transistor TD, then the driving thin film transistor TD is turned ON and the light emitting diode (LED) E emits light. Luminance of the light emitting diode (LED) E is controlled by varying an electric current of the light emitting diode (LED) E, and the storage capacitor CST serves to keep a gate voltage of the driving thin film transistor TD constant while the switching thin film transistor TS is turned OFF. For example, since the driving thin film transistor TD can be driven by a stored voltage in the storage capacitor CST even when the switch thin film transistor TS is turned OFF, the electric current can keep flowing into the light emitting diode (LED) E, and thus the light emitting diode (LED) E emits light until a next image signal is received.
FIG. 2 is a plan view of a basic pixel structure of an active matrix OELD device according the related art. In FIG. 2, a gate line 37 is disposed along a first direction, and a data line 51 and a power line 41 are disposed along a second direction perpendicularly crossing the gate line 37, whereby the power line 41 and the data line 51 define a pixel region P by the crossing of the gate line 37 and a switching thin film transistor TS is disposed near a crossing of the gate and data lines 37 and 51. In addition, a driving thin film transistor TD is located near a crossing of the gate and power lines 37 and 51 next to the switching thin film transistor TS, and a first electrode 58 of a light emitting diode is connected to the driving thin film transistor TD. A storage capacitor CST is disposed over the power line 41 and is comprised of a capacitor electrode 34 to function as a first storage electrode and a portion of the power line PL to function as a second storage electrode. Although not shown in FIG. 2, an organic electroluminescent layer and a second electrode are disposed in series on the first electrode 58. Thus, the area where the first electrode 58 is disposed can be referred to as an organic electroluminescent area.
In FIG. 2, the switching thin film transistor TS includes a first gate electrode 35 that extends from the gate line 37, and a first semiconductor layer 31 that is formed with the capacitor electrode 34. The driving thin film transistor TD includes a second gate electrode 38 and a second semiconductor layer 32, wherein the second semiconductor layer 32 is also formed with the capacitor electrode 34 and the first semiconductor layer 31.
FIG. 3 is a cross sectional view along III—III of FIG. 2 showing a driving thin film transistor, a storage capacitor, and a light emitting diode according to the related art. In FIG. 3, a buffer layer 30 is formed along an entire surface of a substrate 1, both a driving thin film transistor TD and a storage capacitor CST are disposed on the buffer layer 30, and a light emitting diode E is formed over the substrate 1. The driving thin film transistor TD includes a semiconductor layer 32, a gate electrode 38, a source electrode 50, and a drain electrode 52. The storage capacitor CST includes a capacitor electrode 34 and a power line 41 with an interposed insulator 40, wherein the capacitor electrode 34 is formed of the same material as the semiconductor layer 32 during a same process step. The source electrode 50 of the driving thin film transistor TD is connected to the power line 41, and the drain electrode 52 of the thin film transistor TD is connected to a first electrode 58 of the light emitting diode E.
In addition, an organic electroluminescent layer 64 and a second electrode 66 are sequentially disposed on the first electrode 58, wherein the first electrode 58 functions as an anode and the second electrode 66 function as a cathode and both include an opaque metallic material. The first electrode 58, the organic electroluminescent layer 64, and the second electrode 66 constitute a light emitting diode E.
In the OELD device of FIG. 3, there are a plurality of insulators disposed between the conductive layer elements. For example, the buffer layer 30, i.e., a first insulator, is interposed between the substrate 1 and the semiconductor layer 32, and a gate insulator 36, i.e., a second insulator, is interposed between the semiconductor layer and the gate electrode 38. Furthermore, a third insulator 40 is interposed between the capacitor electrode 34 and the power line 41, a fourth insulator 44 is interposed between the power line 41 and the source electrode 50, a fifth insulator 54 is interposed between the drain electrode 52 and the first electrode 58 of the light emitting diode E, and a sixth insulator 60 is interposed between the first electrode 58 and the second electrode 66. Additionally, the third and sixth insulators 40, 44, 54, and 60 have contact holes through which the conductive layer elements electrically communicate with each other.
FIGS. 4A to 4I are cross sectional views showing a fabricating process of the active matrix OELD device of FIG. 3 according to the related art. Many of the patterns shown in FIGS. 4A to 4I are formed through photolithographic processes including photoresist (PR) coating, aligning, exposing, and developing steps using a mask.
In FIG. 4A, after a buffer layer 30 is formed along an entire surface of a substrate 1, first and second semiconductor layers 32 and 34 of polycrystalline silicon are formed on the buffer layer 30 using a first mask process. The first and second polycrystalline semiconductor layers 32 and 34 have island shapes.
In FIG. 4B, an insulator of silicon nitride or silicon oxide and a conductive material of metal are sequentially deposited on the first polycrystalline silicon layer 32, and then patterned using a second mask, thereby sequentially forming a gate insulation layer 36 and a gate electrode 38 on the first polycrystalline semiconductor layer 32. Thereafter, impurities, such as p-type ions or n-type ions, are doped on exposed portions of the first and second polycrystalline semiconductor layers 32 and 34. During the doping process, the gate electrode 38 functions as a mask so that the first polycrystalline semiconductor layer 32 is divided into an active region 32a where the impurities are not doped and drain and source regions 32b and 32c where the impurities are doped. Furthermore, the second polycrystalline semiconductor layer 34 upon which the impurities are fully doped becomes a capacitor electrode, and the drain and source regions 32b and 32c are located on both sides of the active region 32a. 
In FIG. 4C, a first interlayer insulator 40 is formed along an entire surface of the buffer layer 30 to cover the gate electrode 38, the drain and source regions 32b and 32c, and the capacitor electrode 34. Next, a power line 41 of metal is formed using a third mask process on the first interlayer insulator 40 to overlap the capacitor electrode 34. Since the power line 41 is formed directly above the capacitor electrode 34, it forms a storage capacitor with the capacitor electrode 34 and the interposed first interlayer insulator 40.
In FIG. 4D, a second interlayer insulator 44 is formed on the first interlayer insulator 40 and the power line 41. Then, first, second, and third contact holes 46a, 46b, and 46c are formed using a fourth mask process, wherein the first contact hole 46a exposes the drain region 32b, the second contact hole 46b exposes the source region 32c, and the third contact hole 46c exposes the power line 41.
In FIG. 4E, a metal layer is formed on the second interlayer insulator layer 44 and patterned using a fifth mask process, thereby forming a source electrode 50 and a drain electrode 52. The drain electrode 52 contacts the drain region 32b through the first contact hole 46a, and the source electrode 50 contacts the source region 32c through the second contact hole 46b. Furthermore, the source electrode 50 contacts the power line 41 through the third contact hole 46c. 
Accordingly, formation of a driving thin film transistor TD having the semiconductor layer 32, the gate electrode 38, the drain electrode 52 and the source electrode 50 is completed. Moreover, a region corresponding to the power line 41 and the capacitor electrode 34 forms the storage capacitor CST. Although not shown in FIG. 4E, but shown in FIG. 3, the gate electrode 38 of the driving thin film transistor TD is connected to the switching thin film transistor TS, and the power line 41 is disposed parallel to the data line 51.
In FIG. 4F, a first passivation layer 54 having a fourth contact hole 56 resulting from a sixth mask process is formed on the second interlayer insulator 44 while covering the source and drain electrodes 50 and 52. The fourth contact hole 56 exposes a portion of the drain electrode 52.
In FIG. 4G, a transparent conductive material is deposited on the first passivation layer 54. Then, the transparent conductive material is patterned using a seventh mask process, thereby forming a first electrode 58 that contacts the drain electrode 52 through the fourth contact hole 56.
In FIG. 4H, a second passivation layer 60 is formed on the first electrode 58 and the exposed portion of the first passivation layer 54. Then, the second passivation layer 60 is patterned using an eighth mask process, thereby forming an opening 62 that exposes a portion of the first electrode 58. The second passivation layer 60 protects the driving thin film transistor TD from moisture and particles that may exist in the air.
In FIG. 4I, an organic electroluminescent layer 64 is formed on the second passivation layer 60 to contact the first electrode 58 through the opening 62. Then, a second electrode 66 is formed on the organic electroluminescent layer 64 and the exposed portion of the second passivation layer 60 to entirely cover the substrate 1.
The second electrode 66 is formed of an opaque metallic material and acts as cathode, while the first electrode 58 is formed of a transparent conductive material and acts as anode. Moreover, the material for the second electrode 66 should have a small work function in order to easily release the electrons. Therefore, the OELD device of FIG. 4F is a considered a bottom emission-type OELD device that emits light a bottom direction toward the substrate 1.
FIG. 5 is a cross sectional view of an OELD device according to the related art. In FIG. 5, first and second spaced apart substrates 70 and 90, which have inner surfaces facing each other, have a plurality of sub-pixel regions. Then, an array layer 80, which includes a driving thin film transistor (TFT) TD within each sub-pixel region, is formed along an inner surface of the first substrate 70, and a first electrode 72 connected to the driving TFT TD is formed on the array layer 80 within each pixel region. Next, red, green, and blue organic electroluminescent (EL) layers 74 are alternately formed on the first electrode 72, and a second electrode 76 is formed on the organic EL layers 74. Accordingly, the first and second electrodes 72 and 76 and the organic EL layer 74 interposed therebetween constitute an organic EL diode E. The organic EL device shown in FIG. 5 is a bottom-type OELD where light is emitted from the organic EL layer 74 through the first electrode 72 and out of the first substrate 70.
In FIG. 5, the second substrate 90 is used as an encapsulation substrate and includes a concave portion 92 at an inner center portion of the second substrate 90, wherein the concave portion 92 is filled with a moisture absorbent desiccant 94 that removes moisture and oxygen to protect the organic EL diode E. In addition, the inner surface of the second substrate 90 is spaced apart from the second electrode 76, wherein the first and second substrates 70 and 90 are attached with a sealant 85 at a peripheral portion of the first and second substrates 70 and 90 for encapsulation.
In OLED devices according to the related art, a TFT array part and an organic electroluminescent (EL) diode are formed over the same substrate (i.e., a first substrate), and an additional second substrate is attached to the first substrate for encapsulation. However, when the TFT array part and the organic EL diode are formed on one substrate in this way, production yield of the OELD device is determined by a multiplication of the TFT's yield together with the organic EL diode's yield. Since the organic EL diode's yield is relatively low, the production yield of the overall OLED device becomes limited by the organic EL diode's yield. For example, even when a TFT is properly fabricated, the OLED device using a thin film of about 1000 angstroms (Å) thickness can be judged to be inferior due to the defects of an organic electroluminescent layer. This results in loss of materials and increased production costs.
In general, the OLED devices are classified into bottom emission-types and top emission-types according to an emission direction of light used for displaying images via the OELDs. Bottom emission-type OLED devices have the advantage of high encapsulation stability and high process flexibility. However, the bottom emission-type OLED devices are ineffective as high resolution devices since the disposition of the thin film transistors and the storage capacitor formed on the substrate results in poor aperture ratios. In contrast to bottom emission-type OLED devices, top emission-type OLED devices have a higher expected life span because they have simpler circuit layouts that yield high aperture ratios. However, in top emission-type OLED devices, the cathode is generally formed on an organic electroluminescent layer. As a result, transmittance and optical efficiency of a top emission-type OLED device are reduced because of a limited number of materials that may be selected as the cathode. If a thin film-type passivation layer is formed on the cathode to prevent the reduction of the light transmittance, the thin film-type passivation layer can still fail in preventing the infiltration of exterior air into the organic electroluminescent layer.
In the above-mentioned processes forming the organic electroluminescent display device, a plurality of thin film depositions is required, and a plurality of photolithographic processes that use multiple masks are also required. Thus, the repeated processing steps increase the mask process. Since the photolithographic processes include a rinsing process, a photoresist deposition process, an exposure process, a developing process, and an etching process, manufacturing time and production costs can be reduced if only a single mask process is omitted. The OELD device described with reference to FIGS. 4A to 4I, however, requires eight masks, resulting in decreased production yield and increased productions costs. Moreover, the more masks the OELD device requires, the more defects the fabrication process creates.
Additionally, since the active matrix OELD device of the related art includes the thin film transistors and the storage capacitors within the light-emitting direction, it has a decreased rumination area and reduced aperture ratios. In order to overcome these problems, current density should be increased to provided for an increase in luminance of the device, thereby causing a decreased life span of the OELD device.